Encoding:

Format:

SHLLV[_S].PH 

SHLLV.PH   rd, rt, rs

SHLLV_S.PH rd, rt, rs

Purpose:

Shift Left Logical Variable Vector Pair Halfwords

Element-wise left shift of th e two right-most independent halfwords in a vector data t ype by a variable n umber of bits, with optional saturation.

Description:

rd = sign_extend(sat16(rt31..16 << rs3..0) || sat16(rt15..0 << rs3..0))

The two right-most halfword values in register rt are each independently shifted left by shift bits, inserting zeros into the least-significant bit positions emptied by the shift. In the saturating version of the instruction, if the shift results in an overflow the intermediate result is saturated to either the maximum positive or the minimum negative 16-bit value, depending on the sign of the original unshifted value. The two independent results are then written to the corresponding halfword elements of destination register rd.

The sign of the left-most halfword result is extended into the 32 most significant bits of destination register rd.

The four least-significant bits of rs provide the shift value, interpreted as a four-bit unsigned integer; the remaining bits of rs are ignored.

This instruction writes a 1 to bit 22 in the DSPControl register in the ouflag field if any of the l eft shift operations results in an overflow or saturation.

Restrictions:

No data-dependent exceptions are possible.

The operands must be values in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

SHLLV.PH:
   tempB15..0 = shift16Left( GPR[rt]31..16, GPR[rs]3..0 )
   tempA15..0 = shift16Left( GPR[rt]15..0, GPR[rs]3..0 )
   GPR[rd]63..0 = (tempB15)32 || tempB15..0 || tempA15..0
SHLLV_S.PH:
   tempB15..0 = sat16ShiftLeft( GPR[rt]31..16, GPR[rs]3..0 )
   tempA15..0 = sat16ShiftLeft( GPR[rt]15..0, GPR[rs]3..0 )
   GPR[rd]63..0 = (tempB15)32 || tempB15..0 || tempA15..0

Exceptions:

Reserved Instruction, DSP Disabled